VHDL Memory Decoder for BF51x

 In Blackfin, VHDL

This is just a quick snippet of code for you if you happen to be using a Blackfin BF51x processor and have some space and pins on an external FPGA to spare.

There’s a little bit of glue logic needed to make the external M29W320EB flash memory work with the BF51x processor.  It’s only a few gates so if you have a little extra space on an FPGA you are using with it, save your self the items on your BoM and the cost with stocking them and placing them.  While you are at it, don’t forget the external pull-up resistors on the AMS lines.  They may not look necessary from the schematic, but some of the AMS lines are not configured as AMS lines by default.

So, without further adeu, here is the VHDL code:

-- Addressing logic for M29W320EB Flash on BF518 EZBoard
-- Schematics can be found at http://www.analog.com/static/imported-files/eval_kit_manuals/ADSP-BF518F_ezboard_man_rev.1.3.pdf
-- Remember pull-up resistors R13 through R16 on AMS lines
-- without these there can be problems writing and accessing the flash
-- as all AMS lines are not configured as AMS lines by default

-- By Chad Kidder
-- 6 August 2013

library IEEE;

entity BF51x_flash_decode is
Port ( AMS : in  STD_LOGIC_VECTOR (3 downto 0);
A : out  STD_LOGIC_VECTOR (20 downto 19);
CEn : out  STD_LOGIC);
end BF51x_flash_decode;

architecture Behavioral of BF51x_flash_decode is
signal a19s, CEs: STD_LOGIC;
CEn <= a19s and CEs;                        --U25 on EZBoard schematic
a19s <= AMS(0) and AMS(2);                --U23 on EZBoard schematic
A(20) <= not (AMS(2) and AMS(3));    --U13 on EZBoard schematic
A(19) <= a19s;
CEs <= AMS(1) and AMS(3);                --U24 on EZBoard schematic

end Behavioral;

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